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IIT Patna Interview for M.Tech. in Communication Systems

This blog post was originally posted (IIT Patna Interview for M.Tech. in Communication Systems) on the FB Group (GATE Aspirants) –
Prashant Kumar Jha has shared his experience of the IIT Patna M.Tech. interview.
The Panel consisted of 3 Professors.
They asked my introduction.
– I gave.
They handed me with the marker and pointed me to go to the White Board.
Now they asked me Subjects that I’m comfortable with.
Me- Communication Systems, Signals and Systems
Prof- and?
Me-Digital Electronics. ( I don’t know why I said this)
The very first question was.
What is VHDL?
I explained in basic terms and said that I’m only comfortable with basic programming of Combinational Circuits only.
They Asked me to write Code for implementing a MUX.
I did.
Prof- Draw a NAND latch (I did)
Prof- How it is Used to for Debouncing?
Me- Don’t know
Prof- Now write the TT for Full Subtractor and the output Logic.
I Wrote everything but Instead of Borrow by mistake, I had written Carry, so they corrected me and asked me to implement it with 8×1 MUX.
That was the easiest part, I did it within seconds.
Now the Other Prof Who was Simply Listening to me asked me – Do you know what is Root-Locus?
Me-Yes Sir
Prof2- Why it is a Time Domain Analysis?
I thought for a while and said for an OLTF we Draw the Root Locus in which for different Values of K (they asked what is K..Sir Gain Factor) Closed Loops Pole Changes and from that, we can write the Response of the System. Hence it is Time-Domain Analysis.
He Simply Said ‛Yes’
That was not the END yet..
The First Prof again switched to Digital and asked me to draw an Asynchronous Counter Which will Count from 5 to 13.
I said we have to use 4FF with Clock From Q and Negative edge triggered and ‛Clear’ should be used.
Prof- Draw it and explain like a Teacher.
I did but I Put Clear to all the FF.
He again said..Will it be in All FFs?

I realized that starting point was 5 so 0101 and not 0.

So clear only to 1st and 3rd FF.
That was the End.

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